1. 数据分析工程师第1级（Level1）

主要目的：为客户顾问小组提供准确，全面和及时的标准数据分析以解决良率及技术问题。推动公司在数据分析和方法论专长领域的进一步发展。

特殊要求：需出差美国和其它国家 PDF Solutions 分支机构（培训，公司会议等）

工作流程和主要职责:

  • 定位并准备待分析数据。 (测试芯片数据来自于 PDF 的电子测试器，又称 pdFasTest 。)
  • 检查作业传票档案上数据待析日期。与顾问小组协调员协调，跟踪数据待析以开始及时分析。
  • 定位适当的分析报告模板以进行分析。
  • 与数据整合工程师协调，找出并解决数据下载的问题。
  • 执行标准分析报表。
  • 监控分析并与整合工程师协调，共同解决分析运行中的可能出现的任何问题。
  • 检阅分析结果和质量。呈递分析结果给顾问小组协调员及经理。
  • 与工程服务工程师一起解决在分析中遇到的有关数据方面的问题。 上报其他分析中遇到的问题给高级数据分析工程师。
  • 通报客户分析进展情况。
  • 管理并按时完成一组作业。若无法于期限内完成，上报经理。
  • 参与定期操作，质量评估和（分）公司会议。

职位说明:
PDF是半导体业的“医生”，帮助客户发现、分析并解决设计、生产中的疑难杂症，主要集中在生产制造良率和产品性能提高相关的分析研究。数据分析最核心的价值就是发现问题，并对之进行科学分析，一如医生的诊断。提供确切、详尽的诊断分析报告，以及相应的改善建议，是数据分析的职责，为客户发现问题并找出解决方案，是最终的目标。判断数据的完整、正确性，并寻求相关部门作出相应调整也是责任之一，一如拿到X射线报告的医生，首先需要判断这份报告本身的准确性。公司有大量先进分析工具（设计、测试到分析等多个领域），掌握如何使用这些先进工具就像X射线、B超等对医生一样重要。同时，公司一直致力于不断改善和创新，对于这些工具问题的反馈、建议，这也成为数据分析工程师的责任之一。好的诊断不仅在于发现问题，更在于让客户接受并做出相应改进。同时，好的诊断档案对于他人也是良好借鉴，把问题和根源进行清晰、准确的描述并归档，也是数据分析工程师的重要责任。领域知识的复杂多样、爆炸式更新、关联领域的广泛性，快速学习吸收新知识，能根据已有知识背景和新的分析需求，提出建设性意见甚至创造新的分析方法、工具。

职位要求:
学历：电子工程、材料科学 、物理或相关领域的学士，硕士或博士。

语言：通过大学英语四、六级考试。口语及书面英语能满足沟通工作交流及解决技术问题的要求。能以英语撰写报告、文件和电子邮件。能有效地用英语面对面或用电话沟通，流利者更佳。

经验：不需经验，但有半导体产品或工艺数据分析经验者优先考虑。

品格与能力：

  • 优秀的顾客服务态度。注重符合顾客的需求。
  • 优秀的解决技术问题的技能。
  • 自动自发，学习快速。
  • 努力不懈，主动解决问题。
  • 团队精神。能与办公室和远程同事顺利合作。
  • 沟通技巧。能清晰简明地解释并沟通复杂的概念。
  • 彻底而井然有序的工作风格。
  • 非常注意细节。注重准确性。
  • 广泛了解电子，物理和材料科学。更佳: 了解半导体装置物理学，过程技术，和/或 VLSI 设计原理 (CMOS, bipolar, bi-CMOS, DRAM) 。
  • 非常了解实验设计和工程统计学。更佳: 了解统计软件工具(例如 S plus, SAS, RS1, Matlab).
  • 优秀的计算机能力 (UNIX and PC platform)。更佳: 程序语言能力(例如 C / C++, Java)

2. 数据整合工程师第1级（Level1）

主要目的: 为客户顾问小组提供编程，集成及系统管理以解决良率及技术问题。

特殊要求: 需出差美国和其它国家 PDF Solutions 分支机构（培训，公司会议等）

工作流程和主要职责:

  • 建立数据库并作数据输入的准备工作。
  • 将数据输入数据库以便分析。
  • 监控数据输入，处理数据输入错误。
  • 发现并解决数据输入及数据传输中出现的问题。
  • 与数据分析工程师协调，发现并解决数据分析时遇到的数据问题。
  • 监控数据库引擎运作正常。实施常规数据库管理。
  • 实施常规系统管理。
  • 利用多种计算机语言编程来满足分析需求。
  • 参与公司大型编程和集成项目。
  • 通报客户（数据分析工程师，顾问小组等）任务进展情况。
  • 管理并按时完成一组作业。若无法于期限内完成，上报经理。
  • 参与定期操作，质量评估和（分）公司会议。

职位要求:
学历：计算机科学、信息工程或电子工程学科的学士

语言：通过大学英语四、六级考试。口语及书面英语能满足沟通工作交流及解决技术问题的要求。能以英语撰写报告、文件和电子邮件。能有效地用英语面对面或用电话沟通。流利者更佳。

经验：不需经验，但有SQL关系数据库管理系统或大量数据处理经验者优先考虑。

品格与能力：

  • 优秀的顾客服务态度。注重符合顾客的需求。
  • 优秀的解决技术问题的技能。
  • 自动自发，学习快速。
  • 努力不懈，主动解决问题。
  • 团队精神。能与办公室和远程同事顺利合作。
  • 能清晰简明地解释并沟通复杂的概念。
  • 彻底而井然有序的工作风格。
  • 非常注意细节。注重准确性。
  • 具备Unix和 Linux 的实际工作经验。
  • 结构式程序语言（C, C++, Java, Perl）编程能力及快速学习新语言的能力。
  • 熟悉SQL, 关系数据库设计及数据库编程概念。
  • 具备UNIX shell scripts 的经验
  • 对软件开发生命周期的广泛理解。

 

3. CVField Applications Engineer

Education:
MS in EE, Physics, Materials Science, or Chemical Engineering

Job description:

  • Summary: The Characterization Vehicle (CV) test chip, is a core component of PDF yield ramping methodology. The CV test chip Design Engineer conceives, architects and produces these chips; the CV Field Applications Engineer supports these test chips for a client service team and for PDF clients by delivering training for analysis and electrical test tools and supporting these applications at client site.

These are the major responsibilities in this position:

  • Direct client training: To ensure the most effective CV implementation for each client and manufacturing process, the Test Chip Applications Engineer meets client regularly by phone and travels to client sites to to give training classes and supporting new installations of PDF software (pdCV) and test hardware (pdFasTest).
  • Customer Case Tracking and Disposition: First-line support of client questions related to analysis and/or electrical test of the CV test chips. Includes daily use of case-management database (FootPrints) to disposition requests for self and other support groups at PDF.
  • Electrical test data QA: Colloborate with CV Test Engineers to perform QA of first data from each CV and ensure that the CV test chip functions as intended. Beyond simple debugging of test program and mask design issues, this work also results in valuable feedback used guides future CV design efforts.
  • Periodic Maintenance support involving on-site visits to PDF clients
  • Support CV integration: Work closely with CV Integration Engineer to bring-up each CV within a client service engagement including supporting the linkages from electrical test to analysis to client failure analysis and physical review
  • Write training documentation: Write documentation for both internal and external training classes.
  • Travel averages 25% annually.

Required skills and experience:

  • Course work in VLSI physical layout design and/or basic experience in IC layout
  • Functional understanding of basic test structure design, especially for process-related test structures such as Combs, Serpentines, Chains, etc. Experience in more complex test structures (MOSFET, BJT, Antenna evaluation, memory cell evaluation, etc.).
  • Basic understanding of Design-of-Experiment (DOE) techniques and ideas.
  • Basic Understanding of processing steps involved in advanced semiconductor manufacturing processes (e.g., sequence and purpose of typical CMOS processing steps in a DUV, 6LM Cu/DD process)
  • Good computer skills (both UNIX and Windows PC) including familiarity with scripting languages like Perl or Tcl. (No C language experience necessary.)
  • Experience with at least one of the following: 1) Instructing others in Engineering Software Applications (e.g., EDA tools, TCAD tools, Yield Management or Defect Management Systems like dataPOWER); 2) supporting semiconductor electrical test equipment (e.g, Keithley, Agilent, HP) by setting up prober recipes, debugging or writing small test programs and or operating the bench tester or production tester.
  • Excellent written and oral communication skills.
  • Excellent time and project management skills
  • Highly professional, self-motivated and self-managed.

Job desirables:

  • Experience working as a process integration engineer, or understanding of major process integration issues, in advanced semiconductor manufacturing processes (130nm and below)
  • Experience with numerical data analysis for yield or performance characterization of advanced semiconductor manufacturing processes or products. Includes knowledge of basic statistical analysis tools like S-plus, JMP, SAS,etc.
  • Experience supporting or using results of Inline Inspection equipment such as AMAT, KLA-Tencor or Hitachi inline defect inspection or SEM review tools.
  • Experience doing yield or performance modeling of advanced semiconductor manufacturing processes or products, especially in the breakdown of yield loss into module-specific contributions and/or systematic vs. random behavior.
  • Knowledge of specific product or process categories such as High Performance CMOS, ASIC CMOS, DRAM, FLASH, microprocessors, eDRAM processing and NVRAM processing.

 

4. CV Test Chip Layout Engineer
Job description:

  • Design, generate and verify specific Characterization Vehicle? test chip layouts to characterize clients’ manufacturing processes and quantify impact of design on product performance and yield. Focus on short flow (BEOL, FEOL) test chips.
  • Use PDF proprietary automated layout tools including layout generators, routers and packers to create, place and route CV test chip structures.
  • Generate all collateral needed for testing, inspection, analysis, and documentation of CVTest Chips.
  • Participate with client in detailed review of test chip including post-OPC data review and pre mask-making reviews
  • Work closely with PDF CV Analysis Methods to create an optimal design of experiments for CVtest chips.

Required skills and experience:

  • Sound understanding of semiconductor manufacturing process and transistors
  • Experience with semiconductor layout methods and layout tool suites (e.g., Cadence, Mentor, etc).
  • Working knowledge of DRC and LVS tools and deck creation and applicatoin
  • Basic knowledge of Unix scripting languages (e.g., perl, CSH, SH, Tcl, etc)
  • Basic knowledge of parametric test methods
  • Self-motivated and highly professional including some experience with customer interactions
  • Familiarity with interpreting and using Design Rule Manuals for deep sub-micron semiconductor processes (both foundry and IDM)

Job desirables:

  • Experience with Cadence Virtuoso and/or Cadence SKILL programming language
  • Experience with Mentor Graphics Calibre DRC
  • Experience with any part of Design for Manufacturability including design modification, verification, algorithms or failure analysis
  • Experience using circuit modeling software (HSPICE, Spectre, etc)
  • Familiarity with semiconductor reticle-making practices (mask data prep, dummy fill algorithms, basics of OPC, mask fracturing and biasing, etc)

 

5. Software Development Engineer

Why choose PDF?

  • Experience with state of the art semiconductor technology from fabs around the world
  • Broad view of the semiconductor industry
  • Opportunities to innovate and to quickly obtain responsibility
  • High level of impact from individual contribution
  • Working with other high caliber employees
  • Working with ambitious, goal oriented people
  • Exciting, challenging work environment in the silicon infrastructure space
  • Project diversity there is always something new and different to do
  • International travel, 1-2 times a year for 1-2 weeks to the headquarter in San Jose
  • Potential for personal and business growth
  • Patent and paper recognition
  • Competitive pay, annual bonus, stock options

Education:
BS EE/CS, MS EE/CS    

Job description:

  • Developing and supporting a commercial yield simulation tool
  • Developing and supporting in-house tools for design, testing, and analysis of Characterization Vehicle (CV) test chips
  • Developing and maintaining test-suites for quality assurance of the yield simulation tool
  • Writing and maintaining design specification, testing specification, and user’s manual

Required skills and experience: 

  • Strong C++ programming skills
  • A good understanding of object-oriented design principles and advanced C++ concepts
  • Excellent computer skills (UNIX/Windows)
  • Basic UNIX shell scripting skills
  • Excellent written and oral communication skills
  • Fluent spoken and written English
  • Self-motivated team player

Job desirables:  

  • Semiconductor/CMOS fundamentals knowledge
  • Knowledge of EDA and related programming skills
  • Experience with GUI development framework, preferably QT
  • Experience with scripting languages, such as Tcl, Perl
  • Experience with software testing and quality assurance

 

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